1. Field of the Invention
The invention relates generally to methods of manufacturing flash memory devices and, more particularly, to a method of manufacturing a flash memory device minimizing interference between gate lines, reducing stress to memory cells, and improving disturbance of threshold voltages.
2. Discussion of Related Art
In manufacturing transistors or flash memory devices, insulation spacers are formed on sidewalls of gate lines after constructing the gate lines. The insulation spacers are provided to prevent the gate lines from being connected to contact plugs that are subsequently formed. In addition, the insulation spacers are provided to ensure sufficient space between gate lines and source/drain regions in an ion implantation process for forming the source and drain regions in LVPMOS (low voltage PMOS) and LVNMOS (low voltage NMOS) fields. Unless the spaces between the gates lines and the source/drain regions are sufficiently defined, a short channel effect will be generated, which degrades electrical characteristics of the device.
The insulation spacer is usually made of an oxide film and a nitride film. When the spacer is formed of a nitride film, the nitride film is removed after forming source/regions through an ion implantation process. In this case, while there is an advantage of obtaining wider regions for source and drain contacts within the same area than in the case of using an oxide film alone, the nitride film remains at narrow spaces between the gate lines (specifically, wordlines of a NAND flash memory device). The dielectric constant of the nitride film is typically 6 to 8, which is larger than the dielectric constant of the oxide film (e.g., 3.6 to 3.9). Thus, an increase of interference effects between the gate lines and disturbance of threshold voltages results, which will be described in detail as follows.
FIGS. 1A and 1B are diagrams illustrating variations of threshold voltages in memory cells according to bias conditions of peripheral cells.
Referring to FIG. 1A, a string of a NAND flash memory device includes a drain selection transistor (not shown) connected in series between a bitline and a common source line, pluralities of memory cells (nine cells C13 through C21 are shown), and a source selection transistor (not shown). Here, 16, 32, or 64 memory cells are serially connected. This structure of the string is well known, so it will not be described in further detail.
In programming the 16th memory cell C16 in the structure of the string, a wordline assigned to the memory cell C16 is supplied with a pass voltage 10V. Also, a power source voltage or the pass voltage is applied to a selection line of the drain selection transistor and a source selection transistor, and 0V is applied to a bitline (not shown).
When the spacers are formed of the oxide film, the threshold voltage of the programmed memory cell C16 varies by about 0.144V due to interference from the pass voltage applied to the adjacent memory cells C15 and C17. Otherwise, when the spacers are formed of oxide and nitride films, the threshold voltage of the programmed memory cell C16 varies by 0.212V.
Referring to FIG. 1B, it can be seen that when the first memory cell C1 is programmed under the same condition, the interference by its adjacent memory cell C2 relatively decreases to lessen the variation of threshold voltage.
From the foregoing, it can be seen that the first memory cell C1 is less affected from the interference than is cell C16. Also, if the spacer includes a nitride film with a high dielectric constant, the effect of interference is more pronounced, to increase the variation in threshold voltage of the memory cell.